1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a synchronization-type semiconductor memory device such as a synchronous DRAM (Dynamic Random Access Memory) device which operates in synchronism with a clock signal supplied from the outside of the device. More strictly, the present invention is concerned with the refresh operation of the synchronous DRAM device.
Nowadays, various semiconductor memory devices have been proposed and practically used. The integration density of DRAM devices has been drastically increased to 16 Mbits, 64 Mbits and 256 Mbits. With the development of DRAM devices having a large storage capacity, various types of DRAM devices have been proposed in order to meet various requirements. A synchronous DRAM device has been recently proposed which is intended to reduce the cycle time of the serial access and establish the high-speed interface. The synchronous DRAM device is operated in synchronism with an external clock signal and is capable of transferring data at high speed.
2. Description of Prior Art
In the synchronous DRAM, a memory cell array is divided into a plurality of blocks, which are called banks and are operated in the interleaving formation.
FIG. 1 is a block diagram of essential parts of a conventional synchronous DRAM device having four banks #0-#3. A clock buffer 10 outputs internal clock signals on the basis of an external clock signal CLK and a clock control signal CKE. A command decoder 12 decodes a chip select signal /CS ("/" corresponds to the bar marking-above the signal CS shown in FIG. 1), a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE, and generates internal control signals. The signals applied to the command decoder 12 are supplied from the outside the synchronous DRAM devices. An address buffer 14 receives an external address signal having address bits A0-A11 and a refresh address signal supplied from a refresh address counter 24, and selectively outputs these signals to a mode register 20 and a write line driving circuit 26. An I/O data buffer and register 16 temporarily stores data signals DQ0-DQ7 and performs the input/output operation thereon. In the refresh operation, data read from the banks is temporarily stored in the I/O data buffer and register 16 and outputs the read data to the input sides of the banks. A signal DQM controls the outputting of data.
Control signal latch circuits 18 are provided with respect to the four banks #0-#3, and latch the row address strobe signal RAS, the column address strobe signal CAS and the write enable signal WE output by the command decoder 12, and output these signals to the banks #0-#3. For the sake of simplicity, FIG. 1 is illustrated so that the control signals are output to banks #0 and #1 only. A mode register 20 determines an internal operation (for example, the timing of operation) on the basis of the associated control signal from the command decoder 12 and the address signal from the address buffer 14. Column address counters 22 are provided with respect to four banks #0 -#3. Internal counters provided in the counters 22 are operated in response to the address signal, and bit lines of banks #0-#3 are selected.
The refresh address counter 24 generates the refresh address for driving word lines of banks #0-#3 in the refresh operation, and outputs the refresh address to the address buffer 14. A word line driving circuit 26 receives the address signal from the address buffer 14, the control signal from the control signal latch circuit 18 and bank select signals BS0-BS3 from a bank select/latch enable signal circuit 28, and selectively drives the word lines of banks #0-#3. The bank select/latch enable circuit 28 receives the control signal from the command decoder 12 and outputs the bank select signals BS0-BS3 and latch enable signals LE0-LE3 for driving sense amplifiers (which are omitted in FIG. 1) provided in banks #0-#3.
A description will be given, with reference to FIG. 2, of the refresh operation of the synchronous DRAM device shown in FIG. 1.
The external clock signal CLK from the clock buffer 10 is output to the parts of the synchronous DRAM device in the state in which the clock control signal CKE externally supplied from the outside and used to control the internal clock signals is maintained at the high level. The command decoder 12 decodes the chip select signal /CS, the row address strobe signal /RAS and the column address strobe signal /CAS, and outputs a refresh signal REFR (signal indicated by *2 in FIG. 1) to the bank select/latch enable circuit 28 when the received signals all switch to the low level. The bank select/latch enable circuit 28 sequentially outputs the bank select signals BS0-BS3 one by one each time receiving the refresh signal REFR. In the example shown in FIG. 2, the bank select signals BS0-BS3 are output one by one in this order. Further, the bank select/latch enable circuit 28 sequentially outputs the latch enable signals LE0-LE3 each time one of the bank select signals BS0-BS3 is output. In addition to the above-mentioned three control signals, there is a case where the refresh signal is generated using the write enable signal /WE.
The word line driving circuit 26 selects bank #0 in response to the bank select signal BS0, and
selects a word line of bank #0 corresponding to the refresh address received from the refresh address counter 24 via the address buffer 14. Then, the refresh operation is carried out. In the refresh operation, the latch enable signal LE0 is output in response to the bank select signal BS0. The address buffer 14 includes a built-in select circuit, which receives the refresh signal from the command decoder 12 and selects the refresh address. In FIG. 2, although the latch enable signal is depicted so that it is ON, the latch enable signal is disabled at a predetermined timing.
The above operation is repeatedly carried out so that banks #0-#3 are selected one by one, and the word lines are sequentially selected.
However, the synchronous DRAM device described with reference to FIGS. 1 and 2 has the following disadvantages.
The refresh signal REFR determining the refresh operation for each bank is generated from the externally supplied signals, that is, the chip select signal /CS, the row address strobe signal /RAS and the column address strobe signal /CAS. These control signals can be arbitrarily determined by the users of the synchronous DRAM devices.
As the integration density becomes higher, the refresh operation is required to be performed at higher speed. Hence, it is necessary to switch the chip select signal /CS, the row address strobe signal /RAS and the column address strobe signal /CAS at a higher speed to thereby select the four banks one by one at a higher speed. However, the setting of high-speed switching of the chip select signal /CS, the row address strobe signal /RAS and the column address strobe signal /CAS needs a large load of the users and is not desirable. In order to access the four banks one by one in the refresh operation, it is necessary to generate the refresh signal at a high speed four times. Even when the setting of high-speed switching is carried out by the manufacturer, it is very difficult to set the chip select signal /CS, the row address strobe signal /RAS and the column address strobe signal /CAS at a high speed to attempt speeding-up of the operation shown in FIG. 2.